The subject matter relates to a semiconductor design technology, and in particular, to a method for driving a received data in a semiconductor memory device. More particularly, this application relates to a method for driving a received data at a variable data input/output bandwidth in a semiconductor memory device.
Generally, in a semiconductor memory device such as a dynamic random access memory (DRAM), a data input/output bandwidth represents the amount of data that can be simultaneously read or written by one addressing. The data input/output bandwidth makes it possible to perform more efficient operations by controlling the amount of data input/output according to the use purposes of the DRAM. For example, a DRAM used as a main memory might have an X8 data input/output bandwidth, whereas a DRAM used in a graphic card might have an X32 data input/output bandwidth.
Moreover, the data input/output bandwidth corresponds to the number of data input/output pads for the DRAM. For examples the DRAM for the main memory having the X8 data input/output bandwidth has eight data input/output pads, whereas the DRAM for the graphic card having the X32 data input/output bandwidth has thirty-two data input/output pads.
In the case of the DRAM used as the main memory, the data input/output bandwidth may be determined according to whether the DRAM is used in a personal computer (PC) which processes a relatively small amount of data or a server which processes a relatively large amount of data. In one example, a DRAM used in a notebook computer has the X4 data input/output bandwidth, a DRAM used in a desktop computer has the X8 data input/output bandwidth, and a DRAM used in a server has an X16 data input/output bandwidth.
In this way, as the DRAM is used as the main memory, since DRAMs having the same purpose also have a variable data input/output bandwidth, the DRAM used in the main memory is designed to selectively use the X4 data input/output bandwidth, the X8 data input/output bandwidth, and the X16 data input/output bandwidth.
That is, a DRAM is designed which uses the X16 data input/output bandwidth having the sixteen data input/output pads, and this DRAM using the X16 data input/output bandwidth can also be controlled to use only eight or four data input/output pads among the sixteen data input/output pads according to a user's selection, i.e., data input/output option, thereby enabling the DRAM with the X16 data input/output bandwidth to use the X4 data input/output bandwidth and the X8 data input/output bandwidth.
The DRAM used as the main memory can easily change the data input/output bandwidth according to the user's selection, as described above, because the DRAM used as the main memory has the following structure.
FIG. 1 is a block diagram showing a conventional DRAM structure for a main memory.
Referring to FIG. 1, a conventional DRAM for a main memory includes a plurality of banks BANK0 through BANK3, global input/output line GI0 (with sixteen lines) connected to the banks BANK0, BANK1, BANK2 and BANK3 to input and output data, and sixteen data input/output pads DQ0 through DQ15 corresponding to the sixteen lines in global input/output line GI0.
Since the conventional DRAM for the main memory has a structure that all the banks BANK0 through BANK3 are connected to all the data input/output pads DQ0 through DQ15, all the sixteen data input/output pads DQ0 through DQ15 are used in the X16 data input/output bandwidth, only the eight data input/output pads DQ0 through DQ7 are used in the X8 data input/output bandwidth, and only the four data input/output pads DQ0 through DQ3 are used in the X4 data input/output bandwidth. Although the number of data input/output pads used in such a scheme is changed, it is not difficult to input external data to the banks BANK0 through BANK3 via the global input/output line GIO or to output data stored in the banks BANK0 through BANK3.
In this way, the DRAM for the main memory can change the data input/output bandwidth according to a user's selection, whereas a DRAM for a graphics device uses a fixed X32 data input/output bandwidth. This is because the DRAM for the graphics device requires inputting/outputting data at far faster speed than the DRAM for the main memory so that it must have the following structure.
FIG. 2 is a block diagram illustrating a conventional DRAM structure for a graphics device.
Referring to FIG. 2, a conventional DRAM for a graphics device includes a plurality of bank groups 200A through 200D each including a plurality of banks BANK0 through BANK15, a plurality of data input/output pads DQ0 through DQ31 in four groups of eight for respectively receiving data by the bank groups 200A through 200D, and four global input/output lines GI0_UL (with 8 lines), GI0_DL (with 8 lines), GI0_DR (with 8 lines) and GI0_UR (with 8 lines) respectively inputting/outputting data between the bank groups 200A through 200D and four data input/output pad groups 260A through 260D.
As shown in FIG. 2, the data input/output pads DQ0 through DQ31 are divided into the data input/output pad group 260A corresponding to the zeroth bank group 200A, the data input/output pad group 260B corresponding to the first bank group 200B, the data input/output pad group 260C corresponding to the second bank group 200C, and the data input/output pad group 260D corresponding to the third bank group 200D.
The four global input/output lines GI0_UL, GI0_DL, GI0_UR, and GI0_DR are divided into the eight lines of zeroth global input/output line GI0_UL for inputting/outputting data of the zeroth bank group 200A, the eight lines of first global input/output line GI0_DL for inputting/outputting data of the first bank group 200B, the eight lines of second global input/output line GI0_DR for inputting/outputting data of the second bank group 200C, and the eight lines of third global input/output line GI0_UR for inputting/outputting data of the third bank group 200D.
From the structure of the DRAM for the graphics device described above, it can be seen that none of the bank groups 200A, 200B, 200C and 200D is connected to all of the data input/output pads DQ0 through DQ31. That is, the zeroth bank group 200A can input/output data through only the data input/output pad group 260A including the zeroth to seventh data input/output pads DQ0 through DQ7. The first bank group 200B can input/output data through only the data input/output pad group 260B including the eighth to fifteenth data input/output pads DQ8 through DQ15. The second bank group 200C can input/output data through only the data input/output pad group 260C including the sixteenth to twenty-third data input/output pads DQ16 through DQ23. The third bank group 200D can input/output data through only the data input/output pad group 260D including the twenty-fourth to thirty-first data input/output pads DQ24 through DQ31.
Accordingly, in a state where the data input/output bandwidth is changed into the X16 data input/output bandwidth, the second and third bank groups 200C and 200D cannot input/output data, as only the sixteen data input/output pads DQ0 through DQ15 are used.
To provide access to each of the bank groups, even in a case where the number of the data input/output pads for inputting/outputting data is reduced by the change of the data input/output bandwidth, the structure of the DRAM for the graphics device capable of inputting/outputting with all internal banks has been proposed as follows.
FIG. 3 is a block diagram showing a structure of a conventional DRAM for a graphics device, capable of easily changing a data input/output bandwidth.
Referring to FIG. 3, a conventional DRAM for a graphics device capable of changing a data input/output bandwidth includes a plurality of bank groups 300A, 300B, 300C and 300D each including a plurality of banks BANK0 through BANK15, a plurality of data input/output pads DQ0 through DQ31 grouped by a predetermined number for receiving data by each of the bank groups 300A through 300D, first driving units 320A and 320C driving data D0 through D7 and D16 through D23 input through first pad groups 360A and 360C to transfer the data to the first and third bank groups 300A and 300C corresponding to the first pad groups 360A and 360C, second driving units 320B and 320D driving data D8 through D15 and D24 through D31 input through second pad groups 360B and 360D to transfer the data to the second and fourth bank groups 300B and 300D corresponding to the second pad groups 360B and 360D, and data division transferring units 340A and 340B transferring data D0 through D7 and D16 through D23 input through the first pad groups 360A and 360C to the first and third bank groups 300A and 300C corresponding to the first pad groups 360A and 360C and the second and fourth bank groups 300B and 300D corresponding to the second pad groups 360B and 360D.
Moreover, the conventional DRAM for the graphics device further includes first data transferring units 380A and 380C transferring any one of the output data D0 through D7 and D16 through D23 of the first driving units 320A and 320C and the output data D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22 and D23 of the data division transferring units 340A and 340B to the first and third bank groups 300A and 300C corresponding to the first pad groups 360A and 360C in response to an address signal ADDRESS, and second data transferring units 380B and 380D transferring any one of the output data D8, D9, D10, D11, D12, D13, D14, D15, D24, D25, D26, D27, D28, D29, D30 and D31 of the second driving units 320B and 320D and the output data D8, D9, D10, D11, D12, D13, D14, D15, D24, D25, D26, D27, D28, D29, D30 and D31 of the data division transferring units 340A and 340B to the second and fourth bank groups 300B and 300D corresponding to the second pad groups 360B and 360D in response to the address signal ADDRESS.
At this point, the data input/output pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30 and DQ31 are divided into the pad group 360A corresponding to the zeroth bank group 300A, the pad group 360B corresponding to the first bank group 300B, the pad group 360C corresponding to the second bank group 300C, and the pad group 360D corresponding to the third bank group 300D. The pad groups 360A, 360B, 360C and 360D are divided into the first pad groups 360A and 360C, which receive external data regardless of the data input/output bandwidth, and the second pad groups 360B and 360D, which selectively receive data according to the data input/output bandwidth of a semiconductor device.
According to the above-described configuration, in the conventional DRAM for the graphics device capable of changing a data input/output bandwidth, in the operation of the X16 data input/output bandwidth, it can be seen that data are input through the zeroth to seventh data input/output pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 and the sixteenth to twenty-third data input/output pads DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22 and DQ23 included in the first pad groups 360A and 360C whereas data are not input through the eighth to fifteenth data input/output pads DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 and the twenty-fourth to thirty-first data input/output pads DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30 and DQ31 included in the second pad groups 360B and 360D.
Alternatively, in the operation of the X32 data input/output bandwidth, it can be seen that data are input to all the data input/output pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30 and DQ31 included in the first pad groups 360A and 360C and the second pad groups 360B and 360D.
Accordingly, it can be seen that the first driving units 320A and 320C are turned on and drive data input through the first pad groups 360A and 360C, in the operation of the X16 data input/output bandwidth and the operation of the X32 data input/output bandwidth.
On the other hand, it can be seen that the second driving units 320B and 320D are turned off not to perform any operation because data are not input through the second pad groups 360B and 360D in the operation of the X16 data input/output bandwidth, whereas they are turned on and drive data input trough the second pad groups 360B and 360D because data are input through the second pad groups 360B and 360D in the operation of the X32 data input/output bandwidth.
Furthermore, the data division transferring units 340A and 340B simply transfer the data D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22 and D23 input through the first pad groups 360A and 360C to the first and third bank groups 300A and 300C corresponding to the first pad groups 360A and 360C and the second and fourth bank groups 300B and 300D corresponding to the second pad groups 360B and 360D. Such a configuration will be described in more detail below.
FIG. 4 is a circuit diagram illustrating a detailed structure of a conventional DRAM for a graphic capable of easily changing a data input/output bandwidth illustrated in FIG. 3.
FIG. 4 illustrates connection relationships between the zeroth data input/output pad DQ0 included in the first pad groups 360A and 360C, the eighth data input/output pad DQ8 included in the second pad groups 360B and 360D, a zeroth driver DRV0 included in the first driving units 320A and 320C, an eighth driver DRV8 included in the second driving units 320B and 320D, a zeroth path PTH0 included in the data division transferring units 340A and 340B, a zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C, an eighth multiplexer MUX8 included in the second data transferring units 380B and 380D, the zeroth bank group 300A, and the first bank group 300B, among the elements of the conventional DRAM for the graphics device capable of changing the data input/output bandwidth illustrated in FIG. 3.
In FIG. 4, for the convenience of the description, it is omitted to describe to connection relationships of the sixteenth driver DRV16, the sixteenth input/output pad DQ16 and the sixteenth and twenty fourth multiplexers MUX16 and MUX24 shown in FIG. 3, since the sixteenth driver DRV16, the sixteenth input/output pad DQ16 and the sixteenth and twenty fourth multiplexers MUX16 and MUX24 shown in FIG. 3 are corresponding to the zeroth driver DRV0, the zeroth input/output pad DQ0 and the zeroth and eighth multiplexers MUX0 and MUX8 shown in FIG. 3.
Referring to FIG. 4, among the elements of the conventional DRAM for the graphics device capable of changing the data input/output bandwidth illustrated in FIG. 3, the data division transferring units 340A and 340B simply receive the output data of the zeroth driver DRV0 included in the first driving units 320A and 320C and only transfer the zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C and the eighth multiplexer MUX8 included in the second data transferring units 380B and 380D.
That is, when data are output from the zeroth driver DRV0 included in the first driving units 320A and 320C, the data division transferring units 340A and 340B unconditionally transfer the data to the zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C and the eighth multiplexer MUX8 included in the second data transferring units 380B and 380D, and thus the data division transferring units 340A and 340B intend to transfer the output data of the zeroth driver DRV0 included in the first driving units 320A and 320C to the zeroth and first bank groups 300A and 300B.
At this point, in the operation of the X16 data input/output bandwidth, the zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C and the eighth multiplexer MUX8 respectively perform control for the output data of the zeroth path PTH0 included in the data division transferring units 340A and 340B to be transferred to the zeroth bank group 300A or the first bank group 300B in response to the address signal ADDRESS. That is, the zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C and the eighth multiplexer MUX8 respectively perform control for the output data of the zeroth driver DRV0 included in the first driving units 320A and 320C applied to the zeroth path PTH0 included in the data division transferring units 340A and 340B to be transferred the zeroth and first bank groups 300A and 300B.
Similarly, in the operation of the X32 data input/output bandwidth, the zeroth multiplexer MUX0 included in the first data transferring units 380A and 380C and the eighth multiplexer MUX8 respectively perform control for the output data of the zeroth driver DRV0 included in the first driving units 320A and 320C to be transferred to the zeroth bank group 300A and for the output data of the eighth driver DRV8 included in the driving units 320B and 320D to be transferred to the first bank group 300B in response to the address signal ADDRESS.
Additionally, the address signal ADDRESS, which determines whether the output data of the zeroth driver DRV0 is transferred to the zeroth bank group 300A or the first bank group 300B, is applied to an address input pad (not shown) simultaneously with the application of the data D0 of the zeroth data input/output pad DQ0.
Although the data division transferring units 340A and 340B operate with the above-described configuration, when the data input/output bandwidth is changed in the DRAM for the graphics device, data input through a predetermined data input/output pad may instead be driven to be transferred to all banks of the semiconductor memory device.
By the way, as illustrated in FIGS. 3 and 4, it can be seen that the data division transferring units 340A and 340B are disposed relatively near the first driving units 320A and 320C and the first data transferring units 380A and 380C, but is disposed relatively far from the second driving units 320B and 320D and the second data transferring units 380B and 380D.
That is, the first driving units 320A and 320C should transfer data input through the first pad groups 360A and 360C to the relatively near first data transferring units 380A and 380C, and should also transfer data input through the first pad groups 360A and 360C to the relatively far second data transferring units 380B and 380D. Accordingly, the driving power of the first driving units 320A and 320C is relatively strongly designed for the output data thereof to be stably transferred to the relatively far second data transferring units 380B and 380D.
On the other hand, since the second driving units 320B and 320D transfer data input through the second pad groups 360B and 360D to the relatively near second data transferring units 380B and 380D, the second driving units 320B and 320D are designed to have a relatively weak driving power.
In this way, in a case where the driving power of the first driving units 320A and 320C is relatively strongly designed, the driving power of the first driving units 320A and 320C can stably transfer the output data thereof to a far distance, but also consume a large amount of current in proportion to the transferring distance of the output data.
Particularly, in a case where the output data of the first driving units 320A and 320C should stably be transferred to the relatively far first bank group 300B as well as the relatively near zeroth bank group 300A like the operation of the X16 data input/output bandwidth, since it is preferential that data should stably be transferred, the driving power of the first driving units 320A and 320C may strongly be designed.
However, in a case where the output data of the first driving units 320A and 320C are transferred to only the relatively near zeroth bank group 300A and are not transferred to the relatively far first bank group 300B like the operation of the X32 data input/output bandwidth, there is no need that the driving power of the first driving units 320A and 320C is strongly designed.
By the way, the first driving units 320A and 320C have a strong driving power irrespective of the operation of the X16 data input/output bandwidth and the operation of the X32 data input/output bandwidth. Consequently, a current is consumed unnecessarily.